The present invention generally relates to a comparator, and, more particularly, to speed improvements in a bit data comparator.
Comparators have many uses in electronic devices. For example, in order to check an access address to a memory device, a comparator for comparing two address data signals is used. In general, the comparator includes XOR circuits and a logic circuit connected to the XOR circuits. Each XOR circuit detects the coincidence of each data bit. When the two bits coincide, a signal having a logical value of "0" (L level) is output, and when the two bits do not coincide, a signal having a logical value of "1" (H level) is output. The logic circuit receives the output signals from the XOR circuits and determines the coincidence of the two address signals based on whether the logical value of each signal is 0. The logic circuit may be, for example, an n-input NAND circuit.
The n-input NAND circuit includes a number n of pMOS transistors connected in parallel to a power supply and a number n of nMOS transistors connected in series between the pMOS transistors and ground. The output signal of the NAND circuit is obtained from the node between the pMOS transistors and the uppermost stage nMOS transistor. However, since the nMOS transistors are connected in series, the next stage nMOS transistor turns on only when the nMOS transistor near the power supply turns on. Accordingly, the operating speed of the NAND circuit is quite slow.
FIG. 1 is a block diagram of a conventional comparator 10. The comparator 10 compares two 12-bit data words A11 to A0 and B11 to B0. The comparator 10 includes twelve XOR circuits 11A to 11L (only eight XOR circuits are illustrated), three 4-input NOR circuits 12A to 12C (only two NOR circuits are illustrated), one 4-input NAND circuit 13, and an inverter 14.
The XOR circuits 11A to 11L receive the data bits A0 to A11 and the data bits B0 to B11, respectively. When two compared bits coincide, a signal having the logical L level is output, and when the two bits do not coincide, a signal having the logical H level is output.
The 4-input NOR circuit 12A receives the output signals from the XOR circuits 11A to 11D. The 4-input NOR circuit 12B receives the output signals from the XOR circuits 11E to 11H. The 4-input NOR circuit 12C receives the output signals from the XOR circuits 11I to 11L. Each of the 4-input NOR circuits 12A to 12C outputs a signal having the logical L level when any one of the four input signals has the logical H level.
The 4-input NAND circuit 13 receives the output signals from the three 4-input NOR circuits 12A to 12C and outputs an output signal in accordance with a control signal CS. For example, when the control signal CS has the logical H level and all of the output signals from the 4-input NOR circuits 12A to 12C have the logical H levels, the NAND circuit 13 outputs an output signal having the logical L level and the inverter 14 outputs an output signal OUT having the logical H level. In other words, when the two data words coincide and the control signal is high, the NAND circuit 13 outputs a signal having the logical L level.
However, because the comparator 10 has a 2-stage configuration, it does not operate at a very high speed. In particular, as the number of data bits increases, the circuit configuration exceeds 2-stages, so that the operating speed becomes even slower.
Further, in principle, the NOR circuit includes n number of pMOS transistors connected in series to the power supply and n number of nMOS transistors connected in parallel between the pMOS transistors and a ground. Accordingly, as the number of the input signal increases, for example by one, an additional pMOS transistor and an additional nMOS transistor become necessary. As a result, the number of elements increases and the circuit area increases.
It is an object of the present invention to provide a comparator that is relatively fast and does not require an increased elements to compare more data bits.